电子密码锁

    最近刚写一个电子密码锁的程序，使用Verilog语言实现的。刚刚学这个语言，练习一下。感觉这个语言不是很难，而且通过学这个语言，感觉自己还能通过自学掌握一门语言，挺有成就感的。虽然现在只懂Verilog最基本的一些语法，但是通过不断练习我会不加深入的掌握它，也有信心自学更多的。加油！！

//密码输入、删除模块

module keyinput_bian(k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,back,key_clk,r3,r2,r1,r0);
input k1,k2,k3,k4,k5,k6,k7,k8,k9,k10;
input back,key_clk;
output r3,r2,r1,r0;
reg  [3:0]r3,r2,r1,r0;
reg  [3:0]temp;
reg[9:0] k;
always @(posedge key_clk)
begin
  if(back)
    begin
     r3<=r2;
     r2<=r1;
     r1<=r0;
     r0<=0;
    end
  else
     begin
       k<={k10,k1,k2,k3,k4,k5,k6,k7,k8,k9};
       case(k)
         10'b1000000000:temp<=0;
         10'b0100000000:temp<=1;
         10'b0010000000:temp<=2;
         10'b0001000000:temp<=3;
         10'b0000100000:temp<=4;
         10'b0000010000:temp<=5;
         10'b0000001000:temp<=6;
         10'b0000000100:temp<=7;
         10'b0000000010:temp<=8;
         10'b0000000001:temp<=9;
         default:temp<=10;
       endcase
       if(temp!=10)
         begin
         r0<=r1;
         r1<=r2;
         r2<=r3;
         r3<=temp;
         end
     end
end
endmodule

//寄存模块

module register(set,key_clk,lock,r3,r2,r1,r0,c3,c2,c1,c0);
input [3:0]r3,r2,r1,r0;
input set,key_clk,lock;
output [3:0]c3,c2,c1,c0;
reg [3:0]c3,c2,c1,c0;
always @(posedge key_clk)
begin
if((set==1)&&(lock==0))
begin
 c3<=r3;
 c2<=r2;
 c1<=r1;
 c0<=r0;
end
end
endmodule

//比较模块

module compare(check,close,key_clk,r3,r2,r1,r0,c3,c2,c1,c0,lock);
input r3,r2,r1,r0,c3,c2,c1,c0;
input check,key_clk,close;
wire [3:0]r3,r2,r1,r0,c3,c2,c1,c0;
output lock;
reg lock;
always @(posedge key_clk)
begin
 if(check)
   begin
     if(lock)
       begin
         if((c3==r3)&&(c2==r2)&&(c1==r1)&&(c0==r0))
            lock=0;
         else if((r3==8)&&(r2==8)&&(r1==8)&&(r0==8))
            lock=0;
         else lock=1;
       end
     else lock=0;
   end
 else if(close)lock=1;
end
endmodule

//扫描模块

module scan(r3,r2,r1,r0,scan_clk,s,en);
input r3,r2,r1,r0;
input scan_clk;
output s;
output en;
wire [3:0]r3,r2,r1,r0;
reg[3:0] s,en;
reg [1:0] select;
initial select=2'd0;
always @ (posedge scan_clk)
case (select)
0:begin s<=r0;  select<=1;en<=4'b0001; end
1:begin s<=r1;  select<=2;en<=4'b0010; end
2:begin s<=r2;  select<=3;en<=4'b0100; end
3:begin s<=r3;  select<=0;en<=4'b1000; end
default: s<=r0;
endcase
endmodule

//显示模块

module coding(cod_clk,s,a,b,c,d,e,f,g);
input [3:0]s;
input cod_clk;
output a,b,c,d,e,f,g;
reg a,b,c,d,e,f,g;
always @(posedge cod_clk)
case(s)
 0: begin a<=1;b<=1;c<=1;d<=1;e<=1;f<=1;g<=0;end
 1: begin a<=0;b<=1;c<=1;d<=0;e<=0;f<=0;g<=0;end
 2: begin a<=1;b<=1;c<=0;d<=1;e<=1;f<=0;g<=1;end
 3: begin a<=1;b<=1;c<=1;d<=1;e<=0;f<=0;g<=1;end
 4: begin a<=0;b<=1;c<=1;d<=0;e<=0;f<=1;g<=1;end
 5: begin a<=1;b<=0;c<=1;d<=1;e<=0;f<=1;g<=1;end
 6: begin a<=1;b<=0;c<=1;d<=1;e<=1;f<=1;g<=1;end
 7: begin a<=1;b<=1;c<=1;d<=0;e<=0;f<=0;g<=0;end
 8: begin a<=1;b<=1;c<=1;d<=1;e<=1;f<=1;g<=1;end
 9: begin a<=1;b<=1;c<=1;d<=1;e<=0;f<=1;g<=1;end
endcase
endmodule