makefile样本

# source files. SRC = file1.cpp file2.cpp file3.cpp OBJ = $(SRC:.cpp=.o) OUT = ../libutils.a bak# include directories INCLUDES = -I. -I../include/ -I/usr/local/include # C++ compiler flags (-g -O2 -Wall) CCFLAGS = -g # compiler CCC = g++ # library paths LIBS = -L../ -L/usr/local/lib -lm # compile flags LDFLAGS = -g .SUFFIXES: .cpp default: dep $(OUT).cpp.o: $(CCC) $(INCLUDES) $(CCFLAGS) -c $< -o $@ $(OUT): $(OBJ) ar rcs $(OUT) $(OBJ) depend: depdep: makedepend -- $(CFLAGS) -- $(INCLUDES) $(SRC) clean: rm -f $(OBJ) $(OUT) Makefile.bak 

FROM: http://blog.sina.com.cn/s/blog_4fcd1ea301010h26.html