Vrilog HDL 课程设计——数字钟

为了完成小学期的课程设计去图书馆查找资料敲了一个数字钟，一共有四个部分组成

p_clk_div.v

'timescal 1ns/1ns module p_clk_div#(parameter COEFFICIENT = 12,prrameter CNT_WIDTH = 4)(input i_reset_n,input i_clk,output o_div_clk);reg [CNT_WIDTH-1:0]r_cnt;reg r_div_clk;assign o_div_clk = r_div_clk;always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_cnt <= 2'd0;elseif((COEFFICIENT/2 - 1) == r_cnt)r_cnt <= 0;elser_cnt <= r_cnt + 1;endalways@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_div_clk <= 1'b0;elseif((COEFFICIENT/2 - 1) == r_cnt)r_div_clk <= ~r_div_clk;endendmodule

seg_display.v

'timescal 1ns/1nsmodule seg_display(input [3:0]i_data,//定义10位的数据输入input i_dp,output [6:0]o_seg,//定义7位的编码输出，从高到低A、Boutput o_dp);//定义输出信号o_code的缓存reg [6:0]r_seg;assign o_dp = i_dp;assign o_seg = r_seg;always@(*)begincase(i_data)4'b0000: r_seg = 8'hc0;4'b0001: r_seg = 8'hf9;4'b0010: r_seg = 8'ha4;4'b0011: r_seg = 8'hb0;4'b0100: r_seg = 8'h99;4'b0101: r_seg = 8'h92;4'b0110: r_seg = 8'h82;4'b0111: r_seg = 8'hf8;4'b1000: r_seg = 8'h80;4'b1001: r_seg = 8'h90;4'b1010: r_seg = 8'hbf;default: r_seg = 8'hff;endcaseendendmodule

seg_display_ctrl.v

'timescal 1ns/1ns module seg_display_ctrl1(input r_rst_n,input i_clk,input [3:0] i_hour_h,input [3:0] i_hour_l,input [3:0] i_minut_h,input [3:0] i_minut_l,input [3:0] i_second_h,input [3:0] i_second_l,output [7:0] o_seg_control,output [7:0] o_seg_display);reg [3:0]r_display_data;reg [2:0]r_cnt;reg [7:0]r_seg_control;wire w_dp;wire [6:0]w_seg_display;seg_display I_seg_display(.i_data(r_dispaly_data),.i_dp(1'b1),.o_seg(w_seg_display[6:0]),.o_dp(w_dp));always@(posedge i_clk, negedge r_rst_n)beginif(1'b0 == r_rst_n)r_cnt <= 3'd0;elser_cnt <= r_cnt + 3'd1;endalways@(*)begincase(r_cnt)3'd0:r_display_data = i_second_l;3'd1:r_display_data = i_second_h;3'd2:r_display_data = 4'hA;3'd3:r_display_data = i_minut_l;3'd4:r_display_data = i_minut_h;3'd5:r_display_data = 4'hA;3'd6:r_display_data = i_hour_l;3'd7:r_display_data = i_hour_l;defalut:r_display_data = 4'hA;endcaseendalways@(*)begincase(r_cnt)3d'0: r_seg_control = 8b'01111111;3d'1: r_seg_control = 8b'10111111;3d'2: r_seg_control = 8b'11011111;3d'3: r_seg_control = 8b'11101111;3d'4: r_seg_control = 8b'11110111;3d'5: r_seg_control = 8b'11111011;3d'6: r_seg_control = 8b'11111101;3d'7: r_seg_control = 8b'11111110;default:r_seg_control = 8b'11111111;endcaseendendmodule

timer.v

'timescal 1ns/1nsmodule timer(input i_reset_n,input i_clk,output [3:0] o_hour_h,output [3:0] o_hour_l,output [3:0] o_minut_h,output [3:0] o_minut_l,output [3:0] o_second_h,output [3:0] o_second_l,);reg [3:0] r_hour_h;reg [3:0] r_hour_l;reg [3:0] r_minut_h;reg [3:0] r_minut_l;reg [3:0] r_second_h;reg [3:0] r_second_l;assign o_hour_h = r_hour_h;assign o_hour_l = r_hour_l;assign o_minut_h =r_minut_h;assign o_minut_l =r_minut_l;assign o_second_h = r_second_h;assign o_second_l = r_second_l;//秒钟个位加1always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_second_l <= 4'd0;elseif(4'd9 == r_second_l)r_second_l <= 4'd0;elser_second_l <= r_second_l + 4'd1;end//秒钟十位加1always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_second_h <= 4'd0;elseif(4'd9 == r_second_l)if(4'd5 == r_second_h)r_second_h <= 4'd0;elser_second_h <= r_second_h + 4'd1;end//分钟个位加1always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_minut_l <= 4'd0;elseif(4'd9 == r_second_l && 4'd5 == r_second_h)if(4'd9 == r_minut_l || (4'd2 == r_hour_h && 4'd3 == r_hour_l))r_minut_l <= 4'd0;elser_minut_l <= r_minut_l + 4'd1;end//分钟十位加1always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_minut_h <= 4'd0;elseif(4'd9 == r_second_l && 4'd5 == r_second_h && 4'd9 == r_minut_l)if(4'd5 == r_minut_h)r_minut_h <= 4'd0;elser_minut_h <= r_minut_h + 4'd1;end//时钟个位加1always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_hour_l <= 4'd0;elseif(4'd9 == r_second_l && 4'd5 == r_second_h && 4'd9 == r_minut_l && 4'd5 == r_minut_h)if( (4'd9 == r_hour_l) || (4'd2 == r_hour_h && 4'd3 == r_hour_l))r_hour_l <= 4'd0;elser_hour_l <= r_hour_l + 4'd1;end//时钟十位加1always@(posedge i_clk, negedge i_reset_n)beginif(1'b0 == i_reset_n)r_hour_h <= 4'd0;elseif(4'd9 == r_second_l && 4'd5 == r_second_h && 4'd9 == r_minut_l && 4'd5 == r_minut_h && 4'd3 == r_hour_l)beginif(4'd2 == r_hour_h)r_hour_h <= 4'd0;endelsebeginif(4'd9 == r_second_l && 4'd5 == r_second_h && 4'd9 == r_minut_l && 4'd5 == r_minut_h && 4'd9 == r_hour_l)r_hour_h <= r_hour_h + 4'd1;endendendmodule