FIFO的两种输出：时序输出与组合逻辑输出

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对于FIFO的输出有两种：1、输出为时序clk，这样当master发起读信号，一个clk之后有效数据才能传送到master,两个clk时master才能读取有效数据；(但对于此种也可以进行改进，让master一个clk即能读取数据：fifo的输出端保持输出将要被读取的数据，被读取后output next被读取数据，即输出端output尚未读取的数据)

2、输出为组合逻辑，当前clk内有效数据即能传送到master，一个clk时master即能读取有效数据。

下面贴出两种FIFO的code：

第一种输出为timing logic：

`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 07/16/2014 01:32:23 PM// Design Name: // Module Name: round_fifo// Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //////////////////////////////////////////////////////////////////////////////////`define BUF_WIDTH 5    // BUF_SIZE = 16 -> BUF_WIDTH = 4, no. of bits to be used in pointer`define BUF_SIZE ( 1<<`BUF_WIDTH )module round_fifo( clk, rst, buf_in, buf_out, wr_en, rd_en, buf_empty, buf_full, fifo_counter );input                 rst, clk, wr_en, rd_en;   // reset, system clock, write enable and read enable.input [31:0]           buf_in;                   // data input to be pushed to bufferoutput[31:0]           buf_out;                  // port to output the data using pop.output                buf_empty, buf_full;      // buffer empty and full indication output[`BUF_WIDTH :0] fifo_counter;             // number of data pushed in to buffer   reg[31:0]              buf_out;reg                   buf_empty, buf_full;reg[`BUF_WIDTH :0]    fifo_counter;reg[`BUF_WIDTH -1:0]  rd_ptr, wr_ptr;           // pointer to read and write addresses  reg[31:0]              buf_mem[`BUF_SIZE -1 : 0]; //  always @(fifo_counter)begin   buf_empty = (fifo_counter==0);   buf_full = (fifo_counter== `BUF_SIZE);endalways @(posedge clk or posedge rst)begin   if( rst )       fifo_counter <= 0;   else if( (!buf_full && wr_en) && ( !buf_empty && rd_en ) )       fifo_counter <= fifo_counter;   else if( !buf_full && wr_en )       fifo_counter <= fifo_counter + 1;   else if( !buf_empty && rd_en )       fifo_counter <= fifo_counter - 1;   else      fifo_counter <= fifo_counter;endalways @( posedge clk or posedge rst)begin   if( rst )      buf_out <= 0;   else   begin      if( rd_en && !buf_empty )         buf_out <= buf_mem[rd_ptr];      else         buf_out <= buf_out;   endendalways @(posedge clk)begin   if( wr_en && !buf_full )      buf_mem[ wr_ptr ] <= buf_in;   else      buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];endalways@(posedge clk or posedge rst)begin   if( rst )   begin      wr_ptr <= 0;      rd_ptr <= 0;   end   else   begin      if( !buf_full && wr_en )    wr_ptr <= wr_ptr + 1;          else  wr_ptr <= wr_ptr;      if( !buf_empty && rd_en )   rd_ptr <= rd_ptr + 1;      else rd_ptr <= rd_ptr;   endendendmodule

2、输出为组合逻辑，并且此处buf_out即是next output data,master直接读取，rd_en只是控制fifo更新next output data

`define BUF_WIDTH 5    // BUF_SIZE = 16 -> BUF_WIDTH = 4, no. of bits to be used in pointer`define BUF_SIZE ( 1<<`BUF_WIDTH )module round_fifo( clk, rst, buf_in, buf_out, wr_en, rd_en, buf_empty, buf_full, fifo_counter );input                 rst, clk, wr_en, rd_en;   // reset, system clock, write enable and read enable.input [31:0]           buf_in;                   // data input to be pushed to bufferoutput[31:0]           buf_out;                  // port to output the data using pop.output                buf_empty, buf_full;      // buffer empty and full indication output[`BUF_WIDTH :0] fifo_counter;             // number of data pushed in to buffer   reg                   buf_empty, buf_full;reg[`BUF_WIDTH :0]    fifo_counter;reg[`BUF_WIDTH -1:0]  rd_ptr, wr_ptr;           // pointer to read and write addresses  reg[31:0]              buf_mem[`BUF_SIZE -1 : 0]; //  always @(fifo_counter)begin   buf_empty = (fifo_counter==0);   buf_full = (fifo_counter== `BUF_SIZE);endalways @(posedge clk or posedge rst)begin //fifo_counter indicates the state of FIFO, full or empty   if( rst )       fifo_counter <= 0;   else if( (!buf_full && wr_en) && ( !buf_empty && rd_en ) )       fifo_counter <= fifo_counter;   else if( !buf_full && wr_en )       fifo_counter <= fifo_counter + 1;   else if( !buf_empty && rd_en )       fifo_counter <= fifo_counter - 1;   else      fifo_counter <= fifo_counter;endassign buf_out=(!buf_empty&& !rst)?buf_mem[rd_ptr] :'h0;   //read out,next output data, combination logicalways @(posedge clk)begin //write in data   if( wr_en && !buf_full )      buf_mem[ wr_ptr ] <= buf_in;   else      buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];endalways@(posedge clk or posedge rst)begin //modify the pointer of read and write   if( rst )   begin      wr_ptr <= 0;      rd_ptr <= 0;   end   else   begin      if( !buf_full && wr_en )    wr_ptr <= wr_ptr + 1;          else  wr_ptr <= wr_ptr;      if( !buf_empty && rd_en )   rd_ptr <= rd_ptr + 1;      else rd_ptr <= rd_ptr;   endend

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