实验一与门

library ieee;  use ieee.std_logic_1164.all;    entity wss1 is    port     (       a,b: in std_logic;        y:  out std_logic    );    end entity;    architecture rtl of  wss1 is    begin         y   <=a   and   b;    end rtl;  library ieee;use ieee.std_logic_1164.all;entity wss1 isport   (     a,b: in std_logic;      y:  out std_logic  );end entity;architecture rtl of  wss1 isbegin     y   <=a   and   b;end rtl;