卷积运算中5X5卷积模版的实现-verilog

例化4个fifo核，使5X5卷积模版中25个数据同时输出，进而在一个始终内完成卷积运算。
代码如下：

module kernel5x5(clk,rst,a,a11,a12,a13,a14,a15,a21,a22,a23,a24,a25,a31,a32,a33,a34,a35,a41,a42,a43,a44,a45,a51,a52,a53,a54,a55,rd1,wr1,rd2,wr2,rd3,wr3,rd4,wr4,full1,empty1,full2,empty2,full3,empty3,full4,empty4,cnt    );input clk;input rst;input [7:0] a;output [7:0] a11,a12,a13,a14,a15,a21,a22,a23,a24,a25,a31,a32,a33,a34,a35,a41,a42,a43,a44,a45,a51,a52,a53,a54,a55;output rd1,wr1,rd2,wr2,rd3,wr3,rd4,wr4,full1,empty1,full2,empty2,full3,empty3,full4,empty4;output [6:0]cnt;reg [7:0] a11,a12,a13,a14,a21,a22,a23,a24,a25,a31,a32,a33,a34,a35,a41,a42,a43,a44,a45,a51,a52,a53,a54,a55;reg rd1,wr1,rd2,wr2,rd3,wr3,rd4,wr4;reg [6:0]cnt;reg [7:0]a_reg1,a_reg2,a_reg3;wire [7:0]dout1,dout2,dout3;reg [7:0]dout1_reg1,dout1_reg2;reg [7:0]dout2_reg1;fifo1 q1(.clk(clk),.srst(rst),.wr_en(wr1),.rd_en(rd1),.din(a),.dout(dout1),.empty(empty1),.full(full1));fifo2 q2(.clk(clk),.srst(rst),.wr_en(wr2),.rd_en(rd2),.din(dout1),.dout(dout2),.empty(empty2),.full(full2));fifo3 q3(.clk(clk),.srst(rst),.wr_en(wr3),.rd_en(rd3),.din(dout2),.dout(dout3),.empty(empty3),.full(full3));fifo4 q4(.clk(clk),.srst(rst),.wr_en(wr4),.rd_en(rd4),.din(dout3),.dout(a15),.empty(empty4),.full(full4));always@(posedge clk)begin    if(rst)    begin        cnt<=0;rd1<=0;wr1<=0;rd2<=0;wr2<=0;rd3<=0;wr3<=0;rd4<=0;wr4<=0;        a11<=0;a12<=0;a13<=0;a14<=0;        a21<=0;a22<=0;a23<=0;a24<=0;a25<=0;        a31<=0;a32<=0;a33<=0;a34<=0;a35<=0;        a41<=0;a42<=0;a43<=0;a44<=0;a45<=0;        a51<=0;a52<=0;a53<=0;a54<=0;a55<=0;        a_reg1<=0;a_reg2<=0;a_reg3<=0;        dout1_reg1<=0;dout1_reg2<=0;        dout2_reg1<=0;    end    else    begin        wr1<=1;        if(cnt==7'b0001111)        begin            rd1<=1;            wr2<=1;            cnt<=cnt+1;        end        else if(cnt==7'b0011110)        begin            rd2<=1;            wr3<=1;            cnt<=cnt+1;        end        else if(cnt==7'b0101101)        begin            rd3<=1;            wr4<=1;            cnt<=cnt+1;        end        else if(cnt==7'b0111100)        begin            rd4<=1;            cnt<=cnt;            a14<=a15;a13<=a14;a12<=a13;a11<=a12;            a25<=dout3;a24<=a25;a23<=a24;a22<=a23;a21<=a22;            dout2_reg1<=dout2;a35<=dout2_reg1;a34<=a35;a33<=a34;a32<=a33;a31<=a32;            dout1_reg1<=dout1;dout1_reg2<=dout1_reg1;a45<=dout1_reg2;a44<=a45;a43<=a44;a42<=a43;a41<=a42;               a_reg1<=a;a_reg2<=a_reg1;a_reg3<=a_reg2;a55<=a_reg3;a54<=a55;a53<=a54;a52<=a53;a51<=a52;                    end                     else            cnt<=cnt+1;    endendendmodule

仿真图如下：